#include <verilated.h>
#include <Vysyx_22040213_div.h>
#include <verilated_vcd_c.h>
#include <svdpi.h>
#include <verilated_dpi.h>

static Vysyx_22040213_div* top;
VerilatedContext* contextp = NULL;
VerilatedVcdC* tfp = NULL;

void single_cycle(){
	top->clk = 0;top->eval();
	top->clk = 1;top->eval();
	  contextp->timeInc(1);
	  tfp->dump(contextp->time());
}
static void reset(int n) {
  top->rst = 1;
  while (n -- > 0) single_cycle();
  top->rst = 0;
}

void sim_init(){
	contextp = new VerilatedContext;
	top = new Vysyx_22040213_div;
	tfp = new VerilatedVcdC;
	contextp->traceEverOn(true);
	top->trace(tfp,0);
	tfp->open("obj_dir/sim.vcd");

}

void sim_exit(){
	tfp->close();
}
int main() {
  sim_init();
  reset(10);
  long unsigned int dividend[] = {0xfffffffffffffe700,0x1234567887654321,0x0,0x4};
  long unsigned int divisor[]  = {0xa,0x123455678,0x1,0x2};
  for (int i = 0; i< 4;i++){
    top->div_signed = 0b11;
    top->dividend = dividend[i];
    top->divisor = divisor[i];
    top->div_valid = 1;
    single_cycle();
    top->div_valid = 0;
    for(int b = 0; b < 90;b++){
      single_cycle();
      if(top->out_valid){
        if(top->quotient == top->diff_quo && top->remainder == top->diff_rem){
	  printf("ok!\n");
	}
	else{
	  printf("not ok\n");
	}
      }
    }
  }
  sim_exit();
}
